The future is not set in stone, however one thing is guaranteed above all else: in an ever increasing technological world where computers are playing an increasingly important part, Intel will further their domination of the computer market and will make sure that history remembers the EPIC year of 1999. In this report we will discuss the proposals that Intel have put forward for their new Merced 64-bit architecture chip. Also we will compare the differences between Merced and another 64-bit architecture : Alpha 21264 by Digital. Skip to comparison .
Wouldn't it be great if the name Merced was an acronym of More Enhanced Reliable Chips Expertly Developed, instead of being named after a river (which depicts an overflowing basin of useless sediment) in the U.S!
Merced is the name of the new proposed 64-bit architecture that Intel and HP plan to release in 1999 to lead the computer industry into a new generation of micro-processors. It won't be the first of its kind but it will still revolutionise the computer industry because Intel's name is on it. It goes beyond CISC and RISC architectures and is said to be an EPIC discovery (EPIC being Explicitly Parallel Instruction Computing).
Basically the current IA32 architecture has been dissected, inspected, and rectal examined to find out what was the bottlenecks and failings of IA32, so that Intel can carry on their domination of the computer market by developing their usual "need to have" chips.
Well truthfully not a hell of a lot, most of the "new" techniques and technologies have been 'tried and tested' before in other machines. All Intel are doing is putting all of these technologies together in one architecture and coining new names for them to make them sound new and revolutionary.
As mentioned it is a 64-bit architecture - a whole new world than Intel's current 32-bit architecture. It encompasses 40 bit instructions within a 128-bit instruction bundle (see figure 1). If your good at maths you will realise that this will allow 3 instructions to be passed to the compiler at a time - with some bits left over. These left over bits will form the template, which will tell the compiler which instructions (and instruction bundles) can execute in parallel and which ones will have to be executed serially due to dependencies.
As you might realise this puts a heavy dependency on the compiler which is another change. This is probably the most significant feature of IA64 as it is this that makes the majority of decisions about instructions executing in parallel, branch instructions and loading.
One of the problems that all computer architects find is trying to maximise performance at the least cost. A major performance inhibitor in most micro-processors is the wasted clock cycles processing branch misses. Most companies use a complex prediction technique to minimise this problem, however Intel utilises a whole different technique: PREDICATION. . For a detailed description of predication please click here,
Since any load from memory incurrs several clock cycles of latency, any instructions that depend on this data that immediately follow the load have to wait several clock cycles before this loaded data is ready to be used. IA64 uses SPECUALTIVE LOADING to minimise the effect of memory latency. For a detailed description of Speculative Loading please click here; Back-wards compatability
Another major part of the architecture is its backwards compatibility with IA-32 and HP`s PA-RISC software. Intel plan to have both the IA32 instruction set and the new 64 bit instructions both on chip. An internal switch is used to switch between the two instruction sets, and the switching between the instruction sets is said to be very fast. A lot of the new instructions rely heavily on registers. A typical IA32 machine has 8 GPR and 8FPR and a floating point stack. IA64 has 128 GPR and 128 FPR, thus the need to have two separate instruction sets. These new registers, in the IA64, allow greater parallelism due to a bottleneck found in the IA32. It was realised that IA32 did not have near enough registers, thus processes had to queue up to use the registers or sometimes they even had to divert to memory. Although most 64-bit architectures, if not all, are based on workstations, like Digital Alphas, having the backwards compatibility may mean that Intel are planning to produce a PC version of the design, which will bring PC`s into a new age. The most important part of the architecture will definitely be the compiler optimisations, because it will need to detect and correct loading of data, (re-arranging the code to hide latency), and be able to cope with removing branches, (predication).
Now we will compare the differences between the IA-64 proposals and the latest Alpha design, (21264).
If you wish to contact one or both of us then feel free to send e-mails to: - Kenneth Thomson David Stevenson